Bit Serial Arithmetic In Dsp

In this paper we discuss the design and implementation of fixed-function, recursive DSP algorithms. We demonstrate by means of a wave digital lattice filter that a sampling frequency of more than 130 MHz can be achieved for a recursive algorithm by using bit-serial arithmetic. This paper describes the use of digit-serial arithmetic for compact and eecient implementations of real-time DSP applications on eld programmable gate arrays (FPGAs). The results show that digit-serial designs with a digit-size of 2 bits have.

In applications, bit-serial architectures send data one bit at a time, along a single wire, in contrast to architectures, in which data values are sent all bits or a word at once along a group of wires. All computers before 1951, and most of the early machines used a bit-serial architecture—they were. Bit-serial architectures were developed for in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation. Often N serial processors will take less FPGA area and have a higher total performance than a single N-bit parallel processor.

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See also [ ] • • • References [ ]. 61760117514 drajver obnovitj.